The block diagram shows the basic data flow within the Fast IrDA controller.
The Wrapper Unit serves to mark the beginning and end of the IrLAP frame and to check for the reliable transmission of data. Thus the Wrapper Unit appends beginning and ending flags and a Cyclic Redundancy Check (CRC) flag to the IrLAP frame if the controller is transmitting data. It thereby generates the TX frame, which drives the Modulation Unit. If the controller is receiving data, the Wrapper Unit regains the IrLAP frame from the RX frame and examines the CRC. The Modulation Unit modulates the bits of the TX frame from the Wrapper Unit in order to generate the TX signal, thus driving the off-chip IrDA infrared transceiver. The modulation schemes used are Four-Pulse Position Modulation (4PPM) for FIR, and Return Zero Inverted (RZI) for SIR and MIR. The Synchronization Unit detects and synchronizes the RX signal from the off-chip IrDA infrared transceiver. The Demodulation Unit demodulates the synchronized RX signal in order to retrieve the RX frame.
The Baud Rate Generation Unit generates the enable signals en_symb and en_pulse. en_symb determines the symbol rate during transmission. It is also used to sample the RX signal during reception in SIR or MIR mode. The signal en_pulse determines the pulse width during transmission.
The FIFO Unit consists of an n-stage 32-bit shift register as data buffer. Since IrDA supports only half-duplex communication a single buffer can be used for transmission as well for reception of data. The communication between the Fast IrDA Controller and the bus is performed by means of 32-bit registers. Therefore the Bus Interface can easily be adapted to different bus systems.The transfer of the payload data between Fast IrDA Controller and memory can either be controlled by the CPU or by a DMA controller (e.g. ARM PrimeCell DMA Controller (PL080)).
Supported infrared modes and baud rates
Serial Infrared SIR (9.6, 19.2, 38.4, 57.6, 115.2 kbps)
Medium Infrared MIR (0.576 Mbps, 1.152 Mbps)
Fast Infrared FIR (4 Mbps)
Bus Interface
The default configuration of the kernel of the Fast IrDA Controllers includes a generic BPI (Bus Peripheral Interface) that can be easily adapted to more specific interface protocols. Bus width is designed for 32 bits but can be adapted to narrower or wider bus widths.
As of today, two bus interfaces are available: APB and AHB (AMBA).
