The Fast IrDA Core is available as a soft macro. That means it is delivered as VHDL source code. The source code is at RTL (register-transfer-level) and can be simulated and synthesized by standard EDA/CAE tools. The Fast IrDA Core is tested with Mentor Graphic's ModelSim and Synopsys' Design Compiler. The design is prepared for the integration of scan test logic and can be implemented on modern CMOS and FPGA technologies without any timing-related hurdles.
The design is scan-ready, meaning it is prepared for scan insertion (e.g. by Synopsys TestCompiler). Reuse is simple due to the following features:
VHDL soft macro
No latches (level-sensitive flip-flops), only edge-triggered flip-flops
No tristate signals or busses
No technology-dependent cells required
No clock gating, asynchronous logic, combinational feedback loops, etc.
FIR and MIR functionality can be deselected before synthesis
Design Kit
DICE offers a complete design kit consisting of source files, scripts, documentation.
VHDL Source Code
VHDL Packages, Entities, Architectures, Configurations of the entire Fast IrDA Core and the testbench including the test cases as summarized in the documentation of the Fast IrDA Simulation-based Verification Concept.
Documentation
Fast IrDA Controller Product Specification
Fast IrDA Controller Design Documentation
Fast IrDA FPGA Prototype System
Fast IrDA Simulation-based Verification Concept
FPGA Prototyping System
For rapid prototyping tasks, an FPGA-based board is available. The FPGA used is a Xilinx Spartan-II (please refer to www.xilinx.com). It runs at full speed (in this case, 48 MHz), enabling FIR transmission. The FPGA prototyping system has been trimmed for low cost and easy use.
The board is designed to match ARM's Evaluator-7T (http://www.arm.com/devtools/evaluator_7t) and can be plugged piggy-back onto the Evaluator-7T board, which features a ARM7 microcontroller. This facilitates early software development or system evaluation. The Xilinx FPGA hosts the Fast-IrDA core only, whereas the Evaluator-7T represents the entire ARM or microcontroller side.
For further information, please send email to ip-cores_at_dice.at (with _at_ replaced by @)
