Advanced RF transceiver (RF IC) designs making use of energy and area saving digital filtering demand a high performance, high speed digital interface to the baseband IC (BB IC). The DigRF working group specified the DigRF interface according to the following requirements:
Minimize interface pin count
Minimize overall interface power consumption
Provide a very reliable physical layer to eliminate the need for error correction or error detection
Block Diagram
Physical interconnect signals:
SYSCLK (RF IC to BB): single ended
SYSCLK_EN (BB to RF IC): single ended
Tx DataP (BB to RF IC) differential
Tx DataN (BB to RF IC): differential
Rx DataP (RF IC to BB): differential
Rx DataN (RF IC to BB): differential
Phase Correlator:
Responsible for phase recovery by means of the 16-bit synchronization pattern applied on a DigRF frame base
Uses 6 phases of 312MHz in high speed mode
Optimized phase picking for all transmission qualities (minimum eye opening must be 55% according to DigRF V3.09)
Detection of sleep mode request, activation of sleep mode for LVDS line receiver
