We develop multi-million transistor chips with embedded memories, several 32-bit RISC processors, and additional hard-macros. Our main focus is on deep-submicron CMOS circuits for mobile communications. Our main design flow is based on RTL coding by means of VHDL, design verification by both simulation and model checking (formal verification), logic synthesis, scan-test insertion, ATPG, static timing analysis, and test-pattern generation.
Ideally we are looking for experienced design engineers for the development of highly integrated VLSI circuits (ASIC and FPGA) with several years of experience in VHDL (Verilog) coding, both for simulation and synthesis, expertise in the above-mentioned EDA tools, familiar with the software development of hardware-oriented layers (C, C++, Assembler 8/16/32bit).
