 |
|
Contact | Impressum | Sitemap |
|
 |
About |
 |
|
|
Expertise |
|
|
|
Careers |
|
|
|
Press |
|
|
|
Contact |
|
|
|
|
|
|
|
|
|
|
 |
|
 |
|
|
|
|
|
|
|
|
|
|
|
Supported infrared modes and baud rates
- Serial Infrared SIR (9.6, 19.2, 38.4, 57.6, 115.2 kbps)
- Medium Infrared MIR (0.576 Mbps, 1.152 Mbps)
- Fast Infrared FIR (4 Mbps)
|
Feature set
The Fast IrDA controller covers IrDA's IrPHY, except for the optical link (Infrared Transceiver Module, consisting of output driver with LED and infrared sensor/receiver). Thus no software is needed to complete the IrPHY. The following hardware support is implemented:
|
|
- Half-duplex infrared frame transmission and reception
- 16-bit CRC algorithm for SIR and MIR
- 32-bit CRC algorithm for FIR
- Bit and character stuffing
- Preamble, start and stop flag generation
- RZI and 4PPM modulation and demodulation
- Synchronization by means of a DPLL in FIR mode
|
|
|
The bus interface can be adapted easily to different bus systems and is primarily pre-sented as register interface. A register-based FIFO, configurable in size, can be used for buffering the I/O traffic from/to the bus system.
|
|
- Easily adaptable to different bus systems
- 32-bit register interface
- FIFO with configurable FIFO size
- Payload data transfer controllable by CPU or DMA controller
- Optimized for ARM PrimeCell DMA Controller (PL080)
|
Clock Domain
Due to IrDA's nature, the design has a dual-clock approach, typically using 48 MHz for the IrDA core because of the FIR mode (DPLL running at 40, 48, 52, 56 MHz, or 40+n.4 MHz with n=0,1,2,.), and a separate clock domain for the bus interface since most systems are clocked with a specific clock. This dual-clock approach was planned from the beginning of our development of the system, and is reflected in a clean clock domain interface (synchronizing interface).
|
|
|
|
|
|
